AN ABSTRACT OF THE DISSERTATION OF Karthikeyan Reddy for the degree of Doctor of Philosophy in Electrical and Computer Engineering presented on March 10, 2014. Title: Design Techniques For Delta Sigma Modulators Using VCO Based ADCs

approved: Pavan Kumar Hanumolu VCO-based ADCs have recently emerged as attractive alternative to conven­ tional Delta Sigma (ΔΣ) modulator architectures. Few salient features of a VCO­ based ADC are: 1) the quantization noise is 1 order noise shaped, 2) it is an open loop architecture, and, 3) its implementation is mostly digital in nature. Hence, they are ideally suited for oversampled data converter techniques with the capa­ bility to operate at near GHz frequencies. However, their performance is severely limited by the non-linearity of the voltage to frequency transfer curve. Also, when operating at GHz frequencies, the excess loop delay (ELD) of a continuous-time ΔΣ modulator can be a large fraction of the sampling period, thereby affecting the of stability of the modulator. In this work, two new architectures are proposed to overcome the above mentioned drawbacks. In the first approach, a continuous-time Delta Sigma modulator incorporates a non-linear VCO as the second stage in a 2-stage residue canceling quantizer (RCQ) and mitigates the impact of its non-linearity by spanning only a small region of the VCOs tuning curve. In the second approach, both phase and frequency domain information are extracted from the VCO and fedback, which provides an extra clock cycle delay in the feeback path. This relaxes the timing constraints for the modulator, allowing it to be clocked at GHz frequencies.